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(R)
X80200, X80201, X80202, X80203, X80204
Data Sheet January 21, 2005 FN8154.0
Power Supply Sequencer with Power-up System Monitoring
The X80200 power sequencer provides a flexible approach for handling difficult system power-up conditions. The X80200 includes control of up to three voltage supplies and can be cascaded to control additional supplies. The device contains independent undervoltage lockout for each controlled voltage. The three voltage control circuits allow sequencing for primary, core, and I/O voltages. The core and I/O supplies are linked together with a comparator or a timer allowing a tight coupling between these two supplies. The sequencing may be either voltage based or time based. The X80200 contains separate charge pumps to control external N-channel power FETs for each of the supplies. The charge pumps provide the high gate control voltage necessary for efficient operation of the FET switches. The X80200 turns on the primary voltage to the system when the voltage source is steady. This primary FET switch turn-on can be delayed with an external RC circuit. For the secondary voltage sources, the device has a built-in "coreup-first and core-down-last" sequencing logic which is ideal for high performance processors, DSPs and ASICs. The serial bus can be used to monitor the status or turn off each of the external power switches. The X80200 has 3 slave address bits that allow up to 8 devices to be connected to the same bus.
Features
* Sequence three voltage supplies independently - Core and Logic I/O VCC power sequencer for processor supplies - Power up and power down control - Voltage monitors have undervoltage lockout - Internal charge pump drives external N-channel FET switches - Cascadable to sequence more than 3 supplies - Time based or voltage based sequencing * Status register bits monitor gate output status * SMBus compatible Interface * Slave address identification for up to 8 power sequencers (24 supplies) on the same bus * Surface mount 20-pin TSSOP Package
Applications
* Distributed Power Supply Designs * Multi-voltage systems * Multiprocessor systems * Embedded Processor Applications * Digital Signal Processors, FPGAs, ASICs, Memory Controllers * N + 1 Redundant Power Supplies * Support for SSI - Server System Infrastructure Specifications * -48V Hotswap Power Backplane/Distribution * Card Insertion Detection and Power
Pinout
20 LD TSSOP TOP VIEW
SETV REF A0 GND A1 A2 NC SDA SCL READY 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDDL VDDM VDDH VFB DNC GATE_M GATE_H GATE_L ENS GATEH_EN
* Power Sequencing DC-DC Supplies * Databus Power Interfacing * Custom Industrial Power Backplanes * Other: ATE, Data Acquisition, Mass Storage, Servers, Data com, Wireless Basestations
Ordering Information
PART NUMBER X80200V20I X80201V20I X80202V20I X80203V20I X80204V20I UVLOH 4.5 4.5 3.0 3.0 3.0 UVLOM 3.0 2.25 2.25 2.25 0.9 UVLOL 0.9 0.9 1.7 0.9 0.9 PACKAGE TSSOP TSSOP TSSOP TSSOP TSSOP
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
X80200, X80201, X80202, X80203, X80204 Functional Diagram
VDDH 18 VFB 17 DNC 16 GATE_M 15 CHARGE PUMP_M OSC SEQUENCE DELAY LOGIC CHARGE PUMP_H CHARGE PUMP_L 12 ENS CORE-UP-FIRST CORE-DOWN-LAST 11 GATEH_EN 10 READY A0 3 2-WIRE INTERFACE STATUS REGISTER REMOTE SHUTDOWN REGISTER 9 SCL 4 GND 5 A1 6 A2 7 NC 8 SDA GATE_H 14 13 GATE_L
UVLOH VDDM 19 VDDL 20 SETV 1 REF 2 UVLOM UVLOL + -
Pin Descriptions
PIN 1 2 NAME SETV REF DESCRIPTION Set Voltage. This pin is used for voltage based power sequencing of supplies VDDM and VDDL. If unused connect to ground. Reference voltage. This pin is used for voltage based sequencing. The voltage on this pin is compared to the voltage on the VFB pin and provides the threshold for turn on of the GATE_M output. Either a voltage source or external resistor divider can be used to provide the reference. If time based sequencing is used this pin should be tied to VDDH. Slave address pin assignment. It has an Internal pull down resistor. (>10M typical) Voltage Ground. Slave address pin assignment. It has an Internal pull down resistor. (>10M typical) Slave Address pin assignment. It has an Internal pull down resistor. (>10M typical) No internal connections. Serial bus data input/output pin. Serial bus clock input pin. READY Output Pin: This open-drain output pin goes LOW while VDDH is below UVLOH and remains LOW for tPURST after VDDH goes above UVLOH. READY goes HIGH after tPURST.
3 4 5 6 7 8 9 10 11
A0 GND A1 A2 NC SDA SCL READY
GATEH_EN GATE_H Enable. When this pin is HIGH and VDDH > UVLOH the charge pump of the GATE_H pin turns on and the output drives HIGH. When this pin is LOW, the charge pump is disabled and the GATE_H output is LOW. An external RC time delay can be connected between the enable signal and this pin to delay the GATE_H turn on. ENS GATE_L GATE_H GATE_M DNC VFB VDDH VDDM VDDL Enable Sequence. This pin is used for time-based power sequencing of supplies VDDM and VDDL. If unused, connect to ground. GATE_L Output: This output is connected to the gate of an (external) Power Switch "L". The GATE_L pin is driven HIGH when charge pump L is enabled and pulled LOW when the charge pump is disabled. GATE_H Output: This output is connected to the gate of a (external) Power Switch "H". The GATE_H pin driven HIGH when charge pump H is enabled and pulled LOW when the charge pump is disabled. GATE_M Output: This output is connected to the gate of a (external) Power Switch "M". The GATE_M pin driven HIGH when charge pump M is enabled and pulled LOW when the charge pump is disabled. Do not connect (must be left floating). Voltage Feedback Pin. This input pin is used with voltage based power sequencing to monitor the level of a previously turnedon supply. If unused, connect to ground. Primary supply voltage (typically 5V). Monitored Supply Voltage "M" input. Monitored Supply Voltage "L" input.
12 13 14 15 16 17 18 19 20
2
FN8154.0
X80200, X80201, X80202, X80203, X80204
Absolute Maximum Ratings
Temperature under bias . . . . . . . . . . . . . . . . . . . . . .-65C to +135C Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Voltage on given pin (Power Sequencing Functions): All VDD pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7V
Recommended Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 85C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Power Sequencing Control Circuits Over the recommended operating conditions unless otherwise specified
SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DC CHARACTERISTICS - Undervoltage Lockout Comparators VDDH VDDM VDDL IDDH IDDH UVLOH Supply Operating Range Supply Operating Range Supply Operating Range Supply Current Supply Current Undervoltage lockout for VDDH X80200 X80201 X80202 X80203 X80204 UVLOM Undervoltage lockout for VDDM X80200 X80201 X80202 X80203 X80204 UVLOL Undervoltage lockout for VDDL X80200 X80201 X80202 X80203 X80204 VHYS UVLOH,M,L comparator Hysteresis 0.875 0.875 1.65 0.875 0.875 0.9 0.9 1.7 0.9 0.9 30 0.925 0.925 1.75 0.925 0.925 V V V V V mV 2.2 2.2 2.2 2.2 0.875 3.0 2.25 2.25 2.25 0.9 3.05 2.3 2.3 2.3 0.925 V V V V V 4.425 4.425 2.95 2.95 2.95 4.5 4.5 3.0 3.0 3.0 4.575 4.575 3.05 3.05 3.05 V V V V V VDDH = 5.5V VDDH = 3.1V 3.05 0.95 0.95 2.5 200 5.5 5.5 5.5 V V V mA A
DC CHARACTERISTICS - Gates and Others VIH VIL VOL Voltage Input Valid High for ENS, SETV, GATEH_EN Voltage Input Valid Low for ENS, SETV, GATEH_EN Output LOW Voltage (SDA, READY) VDDH x 0.7 -0.5 VDDH + 0.5 VDDH x 0.3 0.4 V V V
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FN8154.0
X80200, X80201, X80202, X80203, X80204
Power Sequencing Control Circuits Over the recommended operating conditions unless otherwise specified (Continued)
SYMBOL VGATE_ON PARAMETER GATE_H, GATE_M GATE_L GATE_H, GATE_M GATE_L VGATE_OFF IGATE_ON IGATE_OFF Gate Voltage Drive (OFF) for GATE_H, GATE_M, GATE_L Gate Current Drive (ON) for GATE_H, GATE_M, GATE_L Gate Sinking Current Drive (OFF) for GATE_H, GATE_M, GATE_L (Note 1) VDDH = 5.5V, VDDM = 0V, VDDL = 0V, GATEH_EN = 0, GATE_H = 5.5, GATE_L = 5.5, GATE_M = 5.5 (Note 1) (Note 1) 25C VDDH = 3.1V TEST CONDITIONS VDDH = 5.5V MIN 9.0 7.0 7.0 6.0 0 20 9 35 10 TYP 10 8 8 7.0 MAX 11.0 9.0 9.0 8.0 0.1 45 11 V A mA V UNIT V
VHYST
VFB comparator
15
20
25
mV
AC CHARACTERISTICS tPURST Delayed READY Output (READY output delayed after VDDH rises above UVLOH) VDDH = 5.5V VDDH = 3.1V VDDH = 5.5V, CGATE = 0 VDDH = 3.1V, CGATE = 0 tDELAY_DOWN VDDH = 5.5V VDDH = 3.1V tOFF GATE_H, GATE_M, GATE_L turn-off time GATE_H, GATE_M, GATE_L turn-on time VDDH Rise Time VDDH Fall Time VDDH = 5.5V, (Note 1) VDDH = 3.1V, (Note 1) VDDH = 5.5V, (Note 1) VDDH = 3.1V, (Note 1) (Note 1) (Note 1) 0.5 2 1.0 1.0 0.6 700 800 600 10 12 40 750 15 80 900 6 900 6 40 80 0.7 5 s ms s ms s s ms ms s s ms
tDELAY_UP
tON
tR tF
VDDH tR tF
GATE_L tDELAY_UP tDELAY_DOWN
GATE_M GATE_H, M, L tON tOFF
UVLOH VDDH tPURST
READY
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FN8154.0
X80200, X80201, X80202, X80203, X80204
Serial bus Interface Electrical Characteristics
SYMBOL VIL VIH VOL CBUS PARAMETER Signal Input Low Voltage Signal Input High Voltage Signal Output Low Voltage Capacitive Load per bus segment (Note 1), Ipullup 4mA (Note 1) 2.0 0.4 400 TEST CONDITIONS MIN MAX 0.8 UNIT V V V pF
Capacitance
SYMBOL COUT CIN NOTE: 1. Guaranteed by device characterization. PARAMETER Output Capacitance (SDA) Input Capacitance (SCL) TEST CONDITIONS VOUT = 0V, (Note 1) VIN = 0V, (Note 1) MAX 8 6 UNIT pF pF
Equivalent AC Output Load Circuit for VDDH = 5V
VDDH 2.06k SDA, READY 30pF
AC Test Conditions
Input pulse levels Input rise and fall times Input and output timing levels Output load VCC x 0.1 to VCC x 0.9 10ns VCC x 0.5 Standard output load
Symbol Chart
WAVEFORM INPUTS Must be steady May change from LOW to HIGH May change from HIGH to LOW Don't Care: Changes Allowed N/A OUTPUTS Will be steady Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedance
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FN8154.0
X80200, X80201, X80202, X80203, X80204 Bus Interface AC Timing
SYMBOL fSCL tCYC tHIGH tLOW tSU:STA tHD:STA tSU:STO tSU:DAT tHD:DAT tR tF tAA tDH TI tBUF tSU:A tHD:A Clock Frequency Clock Cycle Time Clock High Time Clock Low Time Start Set-up Time Start Hold Time Stop Set-up Time SDA Data Input Set-up Time SDA Data Hold Time SCL and SDA Rise Time: TR = (VILMAX - 0.15) to (VIHMIN+0.15) SCL and SDA Fall Time: TF = (VIHMIN - 0.15) to (VILMAX - 0.15) SCL Low to SDA Data Output Valid Time SDA Data Output Hold Time Noise Suppression Time Constant at SCL and SDA inputs Bus Free Time (Prior to Any Transmission) A0, A1, A2 Set-up Time A0, A1, A2 Hold Time (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) 550 300 50 4.7 0 0 PARAMETER TEST CONDITION SMBUS MIN 10 10 4.0 4.7 4.7 4.0 4.0 250 300 1000 300 1100 250 0 50 1.3 0 0 50 MAX 100 2.5 0.6 1.3 0.6 0.6 0.6 100 0 300 300 1100 2-WIRE BUS MIN MAX 400 UNITS kHz s s s s s s ns ns ns ns ns ns ns s ns ns
Timing Diagrams
tBUF tF SCL tSU:STA SDA IN tSU:DAT tHD:STA tHD:DAT tSU:STO tHD:STO tHIGH tLOW tR tBUF
tAA SDA OUT
tDH
tHD:DAT
FIGURE 1. BUS TIMING
START SCL
CLK 1 SLAVE ADDRESS BYTE
CLK 9
SDA IN tSU:A A2, A1, A0 tHD:A
FIGURE 2. ADDRESS PIN TIMING
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FN8154.0
X80200, X80201, X80202, X80203, X80204 Principles of Operation
Power Sequencing Control (PSC)
The Intersil X80200 supports a variety of sequencing applications. The sequencing can be voltage-based or timebased. Some examples are shown in Figure , Figure , and Figure in the Applications section. The X80200 allows for designs that can control the power sequencing of up to three voltage supplies. For systems with more than three supplies, the X80200 may be cascaded. In the absence of an externally provided ENS signal, the ENS pin can be connected in a number of different ways. * ENS can connect to the VDDH pin. In this case, the GATE_H and GATE_L outputs are enabled at the same time. GATE_H could be delayed by using an external RC timer between READY and GATEH_EN to provide a sequence where VDDL is the first supply voltage applied to the system. * ENS can connect to a delayed READY signal, so that the VDDL voltage follows the VDDH voltage by a fixed time. * ENS can connect to the system side of the VDDH FET, so the VDDL voltage will follow immediately after the primary supply is applied to the system. See "Functional Description" on page 7 for details on timing and ramp-up. VOLTAGE-BASED POWER SEQUENCING In this configuration, the drain of the "L" MOSFET is connected to the VFB input of the X80200, the ENS pin is tied to ground and a resistor divider provides a reference voltage to the REF pin. A LOW to HIGH transition of the SETV pin turns on the GATE_L output. This turns on the "L" MOSFET. Once the drain of this FET reaches the REF level, GATE_M turns on. Since the trigger for the GATE_M output is selected by a threshold level, the user has the ability to specify relative core and I/O voltage sequencing.
Basic Functions
VDDH is the primary voltage for the X80200. Once VDDH rises above the primary undervoltage lockout level (UVLOH) for time tPURST, the READY output goes HIGH indicating that the supply power is good. By connecting READY directly to GATEH_EN, the GATE_H output goes high immediately, turning on the power FET connected in series with VDDH. The system primary voltage may be delayed by using an external RC circuit between READY and GATEH_EN. VDDH must be stable before VDDM and VDDL supplies are monitored and power sequencing begins. The second supply voltage (I/O supply) is monitored by the VDDM pin. VDDM must be greater than the I/O supply undervoltage lockout level (UVLOM) prior to any activation of the GATE_M output. The VDDM voltage is used to turn on the charge pump that drives the GATE_M output. The third supply (core supply) is monitored by the VDDL pin. VDDL must be greater than the core supply undervoltage lockout level (UVLOL) prior to any activation of the GATE_L output. The VDDL voltage is used to turn on the charge pump that drives the GATE_M output.
System Monitoring and Remote Shutdown
The X80200 Status Register contains fault detection bits that indicate the status of the GATE_H, GATE_M, and GATE_L pins. These bits are Stat_GATEH, Stat_GATEM, and Stat_GATEL. The status register can be read via 2-wire bus. This feature allows for system monitoring of the power sequencing of supplies. The system can turn off the FETs by writing to the Remote Shutdown Register through the 2-wire interface. There are three turn-off selections. See "Remote Shutdown Register (RSR) (Volatile)" on page 10 for more details.
Power Sequencing Functions
X80200 provides two options for power sequencing. In time based sequencing, the ENS (Enable Sequence) input signals that the core and I/O voltages are to turn on with a fixed time relationship. In voltage based sequencing, the SETV (Set Voltage) initiates turn-on of the core voltage. The I/O voltage remains off until the core voltage reaches a set threshold. In both cases the X80200 uses a core-voltage first and core voltage-last power up/down algorithm. TIME-BASED POWER SEQUENCING A rising edge (LOW to HIGH) transition of the ENS pin turns on the charge pump that drives the GATE_L output. A falling edge (HIGH to LOW) transition of the ENS signal turns off the charge pump that drives the GATE_M output. This technique provides a "forced" core-voltage-first power up and core-voltage-last power down algorithm. The ENS signal does not control the ramp up/down rates of the GATE_M or GATE_L outputs.
Functional Description
Voltage Inputs. The X80200 has three voltage monitors for power sequencing: the VDDH (primary voltage), VDDM (I/O voltage), and VDDL (core voltage). These voltage monitors operate independently of each other. PRIMARY VOLTAGE VDDH This voltage is the primary voltage for the device and is required before X80200 can power sequence VDDM and VDDL. As VDDH powers up, it is compared to an internal UVLOH reference. This undervoltage lockout level is preset at the factory. For information on this setting, see Ordering Information. For custom programmed levels, contact Intersil.
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FN8154.0
X80200, X80201, X80202, X80203, X80204
The READY output pin reflects the condition of the VDDH input. READY is LOW as long as VDDH is below UVLOH and remains LOW for a period of tPURST after VDDH crosses UVLOH, see Figure 4. Once VDDH rises above UVLOH and remains stable for tPURST, the READY output turns ON. If READY connects directly to the GATEH_EN pin, then the GATE_H charge pump turns on immediately. The turn on of the Gate_H charge pump can be delayed by using an external filter (RC filter) connected between the READY and GATEH_EN pins. When VDDH drops below the UVLOH threshold, READY goes inactive immediately. For more details on this turn-off mechanism, See "Power Supply Failure Conditions" on page 9. SECONDARY VOLTAGES VDDM AND VDDL The VDDM and VDDL voltage inputs each have their own undervoltage lockout settings, UVLOM, and UVLOL, respectively. Each undervoltage lockout level is preset at the factory. For information on these settings, See Ordering Information. For custom programmed levels, contact Intersil. The GATE_M and GATE_ L charge pumps are OFF as long as VDDM, and VDDL are below their respective UVLO trip points. When READY is active and VDDM and VDDL go above their UVLO thresholds, the GATE_M and GATE_L charge pumps can be turned ON when activated as part of the power sequence desired. If VDDL or VDDM drop below the UVLO level the charge pumps turn off. For more details on this turn-off mechanism, See "Power Supply Failure Conditions" on page 9. Sequence Delay Logic. This block contains the logic circuits that implement the power-up and power-down sequencing of the VDDH (GATE_H), VDDM (GATE_M), and VDDL (GATE_L) voltages. The sequencing protocol has a built-in "core-first-up and core-down-last" algorithm. On power-up the GATE_L signal turns on first, followed by GATE_M signal. During the power-down, the GATE_M turns off first and the GATE_L signal follows. The sequencing of the power supplies is primarily controlled and regulated via the SETV and the ENS (enable sequence) pins. All charge pumps are designed to ramp up their respective gates at the same slew rate for the same load. time, the GATE_M charge pump turns ON. Again the slew rate is dependent on the load connected to GATE_M output. The falling edge transition on the ENS pin (HIGH to LOW) turns off the charge pump that drives the GATE_M output. After a tDELAY_DOWN time period, the GATE_L charge pump turns OFF.
ENS
GATE_L tDELAY_UP
tDELAY_DOWN
GATE_M
FIGURE 3. TIME BASED SEQUENCING OF GATE_M AND GATE_L
UVLOH VDDH tPURST
READY
FIGURE 4. VDDH/READY SEQUENCING
Voltage Based Power Sequencing (SETV Option)
Using the SETV pin allows for a voltage based sequencing of the GATE_L and GATE_M outputs. SETV is an edge triggered input signal. A LOW to HIGH transition on SETV immediately turns ON the charge pump for GATE_L. The GATE_L output then starts ramping up. In this configuration, the drain of the MOSFET "L" connects to the VFB pin and this voltage is compared to an external reference applied to the REF pin. The comparator turns on the charge pump for GATE_M once the voltage on VFB exceeds the voltage on REF. (See Figure 5.) The voltage sequencing comparator has a 30mV hysteresis, so the GATE_M output does not oscillate as the core voltage powers up. A High to Low transition of SETV turns OFF charge pump M and GATE_M is pulled low. After a tDELAY_DOWN time period, charge pump L turns off and GATE_L is pulled low.
Time Based Power Sequencing (ENS option)
The ENS (Enable Sequence) pin controls the start of the ramp up/ramp down sequence for GATE_M and GATE_L in the time domain. (See Figure 3.) ENS is an edge-triggered input. A rising edge (LOW to HIGH) on the ENS input turns on the charge pump that drives the GATE_L output. The slew rate of the GATE_L output depends on the external MOSFET and any load connected to it. (See Electrical Table). After a tDELAY_UP
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FN8154.0
X80200, X80201, X80202, X80203, X80204
VDDH FAILS VDDM FAILS VDDL FAILS
SETV
VDDH
GATE_L
tDELAY_DOWN
VDDM
REF VDDL FET "L" DRAIN (VFB) REF
GATE_H
GATE_M
FIGURE 5. VOLTAGE BASED SEQUENCING OF GATE_M AND GATE_L
GATE_M
tDELAY_DOWN
Power Supply Failure Conditions
Should there be a power failure of VDDH, GATE_H, GATE_M and GATE_L charge pumps are all turned OFF when VDDH falls below the UVLOH threshold. Should there be a failure of the VDDM supply, the GATE_M charge pump turns off when VDDM falls below the UVLOM threshold. After a tDELAY_DOWN time period, the GATE_L charge pump turns OFF. Should there be a failure of the VDDL supply, the GATE_L and GATE_M charge pumps both turn off when VDDL falls below the UVLOL threshold.
GATE_L
FIGURE 6. GATE CONTROL DURING INDIVIDUAL POWER FAIL CONDITIONS
Remote Monitoring Functions
The X80200 can monitor the status of the GATE_H, GATE_M, and GATE_L charge pump control signals. This allows an indirect way to monitor system voltages. The volatile status bits: Stat_GATEH, Stat_GATEM, and Stat_GATEL indicate the status of GATE_H, GATE_M and GATE_L output control signals, respectively. If the bit is a "1", then the charge pump is being turned on. If the bit is a "0", the output is turned off. Since the bits reflect the internal control signal and not the state of the output, external loading that prevents the charge pump from reaching the desired FET gate drive voltage will not be detected by reading the register. These status bits can be read via the 2-wire serial bus. Refer to Status Register section for more information on how to read this register. Several X80200 devices can be used to monitor many system voltages on different system cards on a backplane. Each X80200 has 3 slave address pins allowing up to 8 X80200 to be used on the same bus. X80200 provides the user the ability to remotely turn-off the gates through software. (See "Remote Shutdown Register (RSR) (Volatile)" on page 10 for more information.)
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FN8154.0
X80200, X80201, X80202, X80203, X80204 Register Information
The Register Block is organized as follows: * Status Register (SR) (1 Byte). Located at address 00h. * Remote Shut Down Register (RSR) (1 Byte). Located at address FFh.
Remote Shutdown Register (RSR) (Volatile)
RSR DATA 01 02 03 GATE SHUTDOWN GATE_M, GATE_L GATE_H GATE_H, GATE_M, GATE_L no override SEQUENCE GATE_M turns off, then after time tDELAY_DOWN GATE_L turns off. Immediate turn off of GATE_H GATE_H and GATE_M turn off, then after time tDELAY_DOWN GATE_L turns off. X80200 returns to previous condition, assuming all supplies are good, GATE_H and GATE_L turn on, then GATE_M turns on according to the chosen sequence mode.
Status Register (Volatile)
7 0 6 0 5 0 4 0 3 STAT_ GATEH 2 STAT_ GATEM 1 STAT_ GATEL 0 WEL
00
The Status Register provides the user a mechanism for checking the status of GATE_H, GATE_M and GATE_L. These bits are volatile and are read only. The gate status values in the Status Register can be read at any time by performing a random read operation. Only one byte is returned by each read operation. The master should supply a stop condition following the output byte to be consistent with the bus protocol. STAT_GATEH: GATEH Status Flag (volatile) STAT_GATEH will be set to `1' when the GATE_H charge pump is turned on. It will be reset to `0' when the GATE_H charge pump is turned off. STAT_GATEM: GATEM Status Flag (volatile) STAT_GATEM will be set to `1' when GATE_M charge pump is turned on. It will be reset to `0' when the GATE_M charge pump is turned off. STAT_GATEL: GATEL Status Flag (volatile) STAT_GATEL will be set to `1' when GATE_L charge pump is turned on. It will be reset to `0' when the GATE_L charge pump is turned off. The status register also contains a WEL bit that controls write operations to the Shutdown Register. Bits 7, 6, 5, and 4 should always be set to `0'. WEL: Write Enable Latch (Volatile) The WEL bit controls the access to the Remote Shutdown Register (RSR). This bit is a volatile latch that powers up in the LOW (disabled) state. While the WEL bit is LOW, writes to the RSR will be ignored (no acknowledge will be issued after the Data Byte). The WEL bit is set by writing a "1" to the WEL bit and zeroes to the other bits of the status register.
The X80200 provides the user with a software shutdown of GATE_H, GATE_L and GATE_M. This over-rides the normal output control. A write operation with data 01h to the RSR will immediately turn off GATE_M followed by GATE_L. The GATE_L turn off is delayed by tDELAY_DOWN. A write operation with data 02 to the RSR will turn off GATE_H. A write operation with data 03 to RSR will shutdown all gates. GATE_H turn off at the same time as GATE_M. GATE_L turns off after a delay of tDELAY_DOWN. A write operation with data 00h to the RSR will remove the software override function. Assuming all supplies are good, the X80200 will return to the previous state by first turning on GATE_H and GATE_L. Then, GATE_M is turned on according to the power sequencing mode chosen. Bits 7, 6, 5, 4, 3 and 2 of the Remote Shutdown Register should always be set to `0'. The data in the RSR can be read by performing a random read operation to the RSR. The data in the RSR powers up in `0' state.
Bus Interface Information
Interface Conventions
The device supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is called the master and the device being controlled is called the slave. The master always initiates data transfers, and provides the clock for both transmit and receive operations. Therefore, the devices in this family operate as slaves in all applications.
10
FN8154.0
X80200, X80201, X80202, X80203, X80204
SERIAL CLOCK AND DATA Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. (See Figure 7.)
Word Address
The next 8 bits following the slave byte, BA7-BA0, determine the portion of the device accessed. If all `0's, then Status Register (SR) is selected. If all `1's, then the Remote Shutdown Register (RSR) is selected.
SCL
Serial Acknowledge
Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. (See Figure 9.) The device will respond with an acknowledge after recognition of a start condition and if the correct Device Identifier and Select bits are contained in the Slave Address Byte. If a write operation is selected, the device will respond with an acknowledge after the receipt of each subsequent eight bit word. The device will acknowledge all incoming data and address bytes, except for the Slave Address Byte when the Device Identifier and/or Select bits are incorrect.
SDA DATA STABLE DATA CHANGE DATA STABLE
FIGURE 7. VALID DATA CHANGES ON THE SDA BUS
SERIAL START CONDITION All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. (See Figure 8.) SERIAL STOP CONDITION All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH, followed by a HIGH to LOW transition on SCL. After going LOW, SCL can stay LOW or return to HIGH. (See Figure 8.)
SCL FROM MASTER DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER
1
8
9
SCL START SDA START STOP ACKNOWLEDGE
FIGURE 9. ACKNOWLEDGE RESPONSE FROM RECEIVER
Write Operation
For a write operation, the device requires the Slave Address Byte and a Word Address Byte. This gives the master access to the registers. After receipt of the Word Address Byte, the device responds with an acknowledge, and awaits the next eight bits of data. After receiving the 8 bits of the Data Byte, the device again responds with an acknowledge. The master then terminates the transfer by generating a stop condition. (See Figure 11, See Figure 1 for bus timing.) In order to perform a write operation to Remote Shutdown Register, the Write Enable Latch (WEL) bit must first be set.
FIGURE 8. VALID START AND STOP CONDITIONS
Slave Address Byte
Following a START condition, the master must output a Slave Address Byte. This byte consists of three parts: * The Device Type Identifier which consists of the most significant four bits of the Slave Address. The Device Type Identifier MUST be set to 1010 in order to select the device. * The next 3 bits (SA3 - SA1) are slave address bits. These bits are compared to the status of the input pins A2-A0. * The Least Significant Bit of the Slave Address (SA0) Byte is the R/W bit. This bit defines the operation to be performed on the device being addressed (as defined in the bits SA2 - SA1). When the R/W bit is "1", then a READ operation is selected. A "0" selects a WRITE operation.
11
FN8154.0
X80200, X80201, X80202, X80203, X80204
Read Operation
A Read operation is initiated in the same manner as a write operation with the exception that the R/W bit of the Slave Address Byte is set to one. Prior to issuing the Slave Address Byte with the R/W bit set to one, the master must first perform a "dummy" write operation. The master issues the start condition and the Slave Address Byte, receives an acknowledge, then issues the Word Address Byte. After acknowledging receipt of the Word Address Byte, the master immediately issues another start condition and the Slave Address Byte with the R/W bit set to one. This is followed by an acknowledge from the device and then by the data byte containing the register contents. The master terminates the read operation by responding with a no-acknowledge and then issuing a stop condition. The ninth clock cycle of the read operation is not a "don't care." To terminate a read operation, the master must either issue a stop condition during the ninth cycle or hold SDA HIGH during the ninth clock cycle and then issue a stop condition. See Figure 12 for the address, acknowledge, and data transfer sequence. See Figure 1 for bus timing.
SLAVE ADDRESS DEVICE TYPE IDENTIFIER SA7 1 SA6 SA5 0 1 INTERNAL DEVICE ADDRESS SA4 SA3 0 A2 SA2 A1 SA1 A0 READ/ WRITE SA0 R/W
Operational Notes
The device powers-up in the following state: * The device is in the low power standby state. * The WEL bit is set to `0'. It is not possible to write to the device. * The WEL bit must be set to allow write operations. * SDA pin is the input mode. * The data in the RSR powers up in `0' state.
BIT SA0 0 1 WORD ADDRESS BA7 0 1 BA6 0 1 BA5 0 1 BA4 0 1 BA3 0 1
OPERATION WRITE READ
BA2 0 1
BA1 0 1
BA0 0 1 SR RSR
DATA BYTE D7 D6 D5 D4 D3 D2 D1 D0
FIGURE 10. ADDRESS FORMAT
12
FN8154.0
X80200, X80201, X80202, X80203, X80204
S T A DEVICE ID R T
SIGNALS FROM THE MASTER
SLAVE ADDRESS
WORD ADDRESS
DATA
S T O P
SDA BUS SIGNALS FROM THE SLAVE
1 0 1 0 A2 A1 A0 0 A C K A C K A C K
FIGURE 11. BYTE WRITE SEQUENCE
SIGNALS FROM THE MASTER
S T DEVICE A ID R T
SLAVE ADDRESS
WORD ADDRESS
S T DEVICE A ID R T
SLAVE ADDRESS
S T O P
SDA BUS
1 0 1 0 A2 A1 A0 0 A C K A C K
1 0 1 0 A2 A1 A0 1 A C K DATA
SIGNALS FROM THE SLAVE
FIGURE 12. READ SEQUENCE
Application Section
DC-DC #1 PRIMARY H (OPTIONAL) I/O VOLTAGES DC-DC #2 M P/ ASICs/ FPGA DC-DC #3 CORE VOLTAGES L CORE SUPPLY SYSTEM COMPONENTS & BOARD SUPPLIES
I/O SUPPLY
-48V BACKPLANE/COMMUNICATION BACKPLANE
HOT SWAP CONTROLLER
X80200 VDDH VDDM REF SETV OPTIONAL RC DELAY VDDL GATEH_EN READY SDA VFB GATE_H VCORE 3.3V 2.7V 2.5V 2.0V 1.8V 1.25V 0.9V V I/O 5V 3.3V 2.5V 1.35V 1.25V Primary 5V
GATE_M GATE_L ENS A0 A2 GND SCL SMBus SLAVE ADDRESS PULL UP TO SET ADDRESS HIGH
SMBus
FIGURE 13. TELECOM BACKPLACE/SYSTEM POWER SUPPLY VOLTAGE BASED POWER SEQUENCING
13
FN8154.0
X80200, X80201, X80202, X80203, X80204
DC-DC #1
PRIMARY H (OPTIONAL) I/O VOLTAGES
SYSTEM COMPONENTS & BOARD SUPPLIES
DC-DC #2
I/O SUPPLY M P/ ASICs/ FPGA CORE SUPPLY L VCORE 3.3V 2.7V 2.5V 2.0V 1.8V 1.25V 0.9V V I/O 5V 3.3V 2.5V 1.35V 1.25V Primary 5V
PGOOD1
HOT SWAP CONTROLLER
DC-DC #3
CORE VOLTAGES
PGOOD2
-48V BACKPLANE/COMMUNICATION BACKPLANE
VDDH VDDM REF SETV OPTIONAL DELAY VDDL
VFB
GATE_H
GATE_M GATE_L ENS A0 A2 GND SCL SMBus SLAVE ADDRESS
GATEH_EN READY SDA
PULL UP TO SET ADDRESS HIGH
OPTION FORCED SEQUENCING
SMBus
FIGURE 14. TELECOM BACKPLACE/SYSTEM POWER SUPPLY TIME BASED POWER SEQUENCING
14
FN8154.0
X80200, X80201, X80202, X80203, X80204
POWER SEQUENCING (TIME BASED MODE) USING POWER GOOD SIGNALS
DC-DC #1
PRIMARY H (OPTIONAL) V I/O PGOOD1 M
SYSTEM COMPONENTS & BOARD SUPPLIES
DC-DC #2 7,8,55-57 VID4:ID0 VRM POWER SUPPLY 10 PWRGD VCORE 53 OUTEN
I/O SUPPLY
VID4:IDO
P/ ASICs/ FPGA
CORE SUPPLY
X80200 VDDH VDDM 5 SCL 9 SDA REF SETV OPTION DELAY VDDL GATEH_EN READY SDA SMBus VFB GATE_H
GATE_M GATE_L ENS A0 A2 GND SCL SLAVE ADDRESS PULL UP TO SET ADDRESS HIGH NC
VCORE 3.3V 2.7V 2.5V 2.0V 1.8V 1.25V 0.9V
V I/O Primary 5V 5V 3.3V 2.5V 1.35V 1.25V
OPTIONAL FORCED SEQUENCING
SMBus
FIGURE 15. POWER SEQUENCING OF VRM SUPPLIES
15
FN8154.0
X80200, X80201, X80202, X80203, X80204 Packaging Information
20-Lead Plastic, TSSOP, Package Code V20
.025 (.65) BSC
.169 (4.3) .252 (6.4) BSC .177 (4.5)
.252 (6.4) .260 (6.6)
.041 (1.05) .0075 (.19) .0118 (.30)
.002 (.05) .006 (.15)
.010 (.25) Gage Plane 0 - 8 .019 (.50) .029 (.75) Detail A (20X) Seating Plane
.031 (.80) .041 (1.05) See Detail "A"
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 16
FN8154.0

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